Description
ASIC Design Engineer - *ASAP Start* - Stuttgart, Germany – 6 Months - 80 EUR/hrOptimus Search are currently recruiting for a talented ASIC design engineer to join a rapidly expanding semiconductor company based in the Stuttgart.
You will be responsible for developing digital circuit components in CMOS technology for sensors
Responsibilities:
• Develop digital functions in VHDL
• Perform RTL synthesis and verification
• Integration in consultation with analog engineers
• Support chip development through to tape out
Experience:
• Degree educated in electrical engineering or similar
• Strong background in RTL design with VHDL/Verilog
• Experience in constraint and script base synthesis
• Experience with verification of synthesis steps (e.g. scan chain insertion knowledge of place and route)
• Excellent communication skills in English