RC

Razvan Chichianu

available

Last update: 28.01.2019

Senior ASIC Verification Engineer

Graduation: MSc. Analogue and Digital ASIC design
Hourly-/Daily rates: show
Languages: English (Full Professional) | Romanian (Native or Bilingual)

Keywords

Functional Testing Specman SystemVerilog Hardworking and Dedicated

Attachments

razvan-chichianu.pdf

Skills

5+ years of functional verification experience
Extensive practical knowledge in Specman Practical knowledge in System Verilog
I ramp up fast and I'm pretty good at verification 
Hard-working
 

Project history

F1 A0 verification (started):
256Gb PCIe gen 5 NIC
Working on PCIe related block and sub-chip level verification, register model
E5 A0 verification:
256Gb PCIe gen 4 NIC
Worked on PCIe related block and sub-chip level verification
AH A0 verification:
100Gb PCIe gen 3 NIC
Worked on PCIe related block and sub-chip level verification, other misc small blocks
E4 B0 verification:
100Gb PCIe gen 3 NIC
Worked on PCIe related block and sub-chip level verification, other misc small blocks

Local Availability

Only available in these countries: Romania
Looking for remote work. Travel up to 50%.
Profileimage by Razvan Chichianu Senior ASIC Verification Engineer from Senior ASIC Verification Engineer
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