HP

henrik pedersen

available

Last update: 06.09.2022

Senior Principal ASIC Specialist Consultant

Graduation: MSC
Hourly-/Daily rates: show
Languages: German (Elementary) | English (Full Professional) | French (Elementary)

Attachments

henrik m pedersen Resume Febuary 2020.pdf

Skills

ASIC, LTE, Radon1.1, Krypton, Shark, code coverage, Scrum, Jenkins, c++, HLS, Cortex M3, peripherals, spread sheet, NFC, continuous integration, FPGA, hardware accelerator, environment, Python scripting, PCIe, virtualization, Modem, Viterbi, DSP algorithm, power compiler, DC, PrimeTime, PrimeTime PX, power estimation, Test automation, Test Suite, Hardware Design, Altera, VHDL, FFT, 1Gb/s Trispeed TCI/IP streaming, VITA Protocol, Ethernet, JTAG, speed test, signal processing, SimuLink, pipelining, STM, SDH, PLL, EMC, System design

Project history

03/2017 - 03/2018
Expert ASIC Consultant
Huawei

5G LTE direct mode transmitter verification:


* tx-top-level verification strategy
* create register layer UVM testbench with cycle and bit accurate verification towards c++ reference,
* constraint random verification to achieve coverage goals functional and code coverage
* setup Jenkins in Leuven site for continous integration
* setup vManager for regression
* top level integration
* gate level simulations




MIPI Front end module verification:


* Create UVM testbench to support new features
* setup vManager for regression
* gate level simulations



Define next digital architecture
* Support of LO/2 to give better spectral performance compared with LO/3
* Re-architect clock tree
* Re-architect digital processing up-sampling chain to reduce power by approximately 50%
* HLS synthesis of DPD module
* Formal verification of IP blocks

08/2016 - 03/2017
Senior Principal ASIC Specialist Consultant
EnSilica

Architectural specification of an ARM Cortex M3 mixed signal SOC for a lithium battery charger
:
Development of the target IC Specification
Development of the mixed signal architecture design specification
IP selection - peripherals, bus interconnection, NVM, SRAM, standard cell IP selection
Maintain area/power excel spread sheet Defining analogue and digital interfaces
top-level verification strategy
Timescales, costing and risks the development
Outline of DFT test strategy

Architectural definition and digital technical lead of NFC powered smart card mixed signal SOC
with Cadence BBE16EP DSP:
Requirement management with customer
Development of the architecture design specification, optimise memory architecture Define
clock gating strategy
Illustrate potential benefits of using DVFS techniques on total power
Generate and maintain full list if IP requirements, including vendor options where available,
Setup NDA
IP selection - peripherals, bus interconnection, NVM, SRAM, standard cell IP selection
Maintain area/power excel spread sheet
Risk management of the development
Outline of DFT test strategy
Technical lead of digital development
Clock, reset and power management implementation
Cadence BBE16EP connectivity and integration
Top level integration
Setup Jenkins for continuous integration FPGA
prototyping

09/2015 - 08/2016
Senior Design Engineer
Sensium HealthCare

Sensium Healthcare develops wireless solutions, offering is SensiumVitals®, a wireless system
for measuring the vital signs of patients in general wards and A&E departments.


Wireless ARC based SOC RTL development inclusing WBAN 802.15.6 development, PMU, clock
distribution, AES CCM, security engine, NSP legacy low power wireless protocol, dedicated low
power heart rate hardware accelerator, SRAM arbitration, APB / ADC and RF interfaces.


Development of corresponding block level UVM register layer verification against reference
models. Setting up Jenkins regression environment including Python scripting development.


Setting up Synopsys and Cadence synthesis and power compiler flow.

Frontier Microsystems employees (the silicon team) are at risk of redundancy following the
decision of the Board to close Frontier Microsystems, after TSC's funding to acquire Frontier
microsystems fell through. All ASIC development has been put on hold for now.

12/2013 - 09/2015
Principal Engineer
Micron Technology

PCIe connected storage virtualization of ACHI and NVMe solid state devices. Verification
of ACHI Virtualization Layers implemented in FPGA's. NVMe Error management and
High availability architecture of NVMe Virtualization Layers for storage enterprise
Systems.
Advanced NVMe SSD controller design of bleeding edge SXP

11/2010 - 12/2013
Senior Asic Specialist
Renesas Mobile Corporation

ASIC Front end designer of GSM, LTE, 3G and DigRF IP in Wireless Modem SOC. Most
focus on Viterbi decoders enhanced SISO and advanced List. Low power optimizations
particularly in the GSM modem.
Digital front-end tech lead of RFIC digital development, coordination of several sites, low
power / area design optimizations, including Clock tree optimization and power gating /
power aware verification, DSP algorithm optimization and implementation. Extensive
use of Synopsys ASIC tool flow, (power compiler, DC, PrimeTime, PrimeTime PX,and
Magma ASIC tool flow (Conformal, Blast).
UPF Power aware simulations with VCS, power reduction and power estimation
Power estimation and reduction (PowerTheater, PowerArtist) , MVRC Power Gating
Pipe cleaning,
Test automation (Jenkins) and Test Bench / Test Suite Qualification with Certitude
(SpringSoft)

11/2007 - 11/2010
ASIC Specialist
Nokia

ASIC Front end designer of GSM, LTE, 3G and DigRF IP in Wireless Modem SOC. Most
focus on Viterbi decoders enhanced with advanced List. Low power optimizations
particularly in the GSM modem.

11/2004 - 11/2007
Hardware Design Engineer
Weibel Scientific

Hardware designer and system architect of digital Radar processing boards, with Altera
or Xilinx FPGA's.
VHDL/RTL design of dedicated FFT engines, FIR Filters, CORDIC engines, 1Gb/s Trispeed
TCI/IP streaming, VITA Protocol over fiber channel, 200 MHz DDR-II SDRAM, Dual
FPGA Embedded Power PC software development.

10/2000 - 11/2004
Design Engineer
Vitesse Semiconductor is now Microsemi; ASIC

Front-end RTL Design of Ethernet MAC's: Campbell-I, Meigs-IIe, Barrington. GFPT over
fiber channel. Production testing of Barrington:, JTAG, MBist and at-speed test
vectors, proven in GLS. The MAC products are listed at:
http://www.vitesse.com/products/bygroup.php.

10/1998 - 10/2000
Student
Technical University of Denmark

Industrial Phd Student, (Terminated before graduation).
Fast signal processing with FPGA Devices in Medical 3D Ultrasound.
6 months Internship at Xilinx piloting QAM and QPSK IP Cores. SimuLink simulation and
bit accurate RTL Design of Channel Equalizers with various pipelining designs.

05/1995 - 10/1998
Hardware Design Engineer
DSC Communications

Hardware board design of STM-16 modules with switching capabilities to STM-1 (SDH

2.5 Gb/s), including PLL, EMC, RF, FPGA, Opto electronic STM-16, EMC compliance
testing.

04/1994 - 04/1995
Young Graduate Trainee
European Space Agency

System design of a P-Band SAR for global climate measurements. The work has
included: A scientific requirement specification, development of software in C and Lab
Windows to design an optimal "phased array" antenna in the elevation plane,
simulation of the radar with an upgraded version of SPAM (A software packet
developed to the design of the AMI'en in ERS-1 ).

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