Sivasubramanian Manickam available

Sivasubramanian Manickam

Senior engineer

Profileimage by Sivasubramanian Manickam Senior engineer from
  • Freelancer in
  • Graduation: masters
  • Hourly-/Daily rates:
  • Languages: Arabic (Native or Bilingual) | English (Limited professional)
  • Last update: 19.10.2020
CV - Sivasubramanian Manickam

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network engine, ASIC Design/Verification, Verilog, FPGA Hardware, ASIC, parsing, SynopsysVCS, VERDI, Cadence Xcelium, Questa ModelSIM v10.0d, Questa SIM v10.2c, cadence nc-sim, Xilinx ISE 14.4i, Xilinx Vivado ALTERA Quartus II 12.0, Synopsys Metaware Debugger, IBM PPC440, ARM CortexM, GREBE, SYNOPSYS ARC, UART, I2C, I3C, SPI, SPEEDY, I2S, AMBA APB, AHB, AXI, IBM PLB, AXI Interconnects, ARM LongHops, TREX, HVL, System Verilog, UVM, Operating System, Linux, Windows, UBOOT, Scripting Languages, Perl, TCL, Neural Network, augmented reality, algorithms, object detection, power efficiency, ASIP, Memory management, DMA, user interface, image processing, CAFFE, FPGA, algorithm, Altera, decoding, firmware, LDPC algorithm/SanDisk LDPC algorithm, Quartus, PCIe, Microblaze, PowerPC, VIRTEX 5 FPGA device, debugging, Flash Memory, X0Y0, Bit File, API, SDK, U-Boot, Regression, TCL script, Perl scripts, Questa simulation, XSDK, co-hardware, software simulation, IBM, Boot Loader, Embedded Hardware, shell script, test case, bug tracker, Vivado, shell, script, boot file, windows shell, Xilinx ISE, Modelsim, Ethernet, PCI, MAC address, QuestaSim10.0b
  • 04/2016 - 12/2017

    • Synopsys India Private Limited; Cerium Systems Private Limited
  • Senior Engineer
  • Project 2
    Project SOC Verification of Convolution Neural Network Engine with ARC processors.

    Client Synopsys India Private Limited, Hyderabad
    Employer Cerium Systems Private Limited, Bangalore
    Hardware ARC HS cluster Processor, AMBA AXI, Convolution Neural Network Engine
    Role Senior Engineer
    Team Size 5
    Duration 1.7 years [Apr'2016 to Dec'2017]
    New DesignWare EV6x processors deliver up to 100X higher performance on common vision processing
    tasks than the previous generation EV5x vision processors to address high throughput applications
    such as ADAS, video surveillance and virtual/augmented reality. New scalable vector DSP architecture
    supports full range of vision algorithms for 1080p to 4K resolutions to meet high definition
    requirements. Programmable convolution neural network provides up to 800 MACs/cycle for fast and
    accurate object detection and 5X better power efficiency than other vision processors

    * AXI VIP Integration for MLV environment and SLV Environment (UVM).
    * Worked on C-based verification, MLV test cases in C for TNN ASIP processors.(Dual Processor
    core). Enhanced thread management. Memory management with DMA-AXI transfers.
    * Worked on writing C test cases for SOC environment from scratch for ARC HS cluster (4 ARC
    processor +APEX for user interface).
    * Worked on Randomization to randomize the image pixel values, Convolution co-efficient for
    CNN engine.
    * Worked on checking the image processing algorithms.
    * Have good experience on handling the images in memory, Techniques involved in image
    processing to handle it for Convolution neural network.
    * Presently working on creating reference functions for verification using
    "CAFFE' model from Berkeley University.
    It involves giving generating the ".caffe model and .prototxt" file for "EVGENCNN" tool of
    Synopsys and testing them for randomized graphs, generate the Weights and graph with OPENVX
    library to test them in CNN ASIP engine. It is being done in both PLV, MLV, SOC level.

    Languages and Tools Verilog, C, Synopsys Metaware Debugger, System Verilog, UVM, DPI, simulation using VCS, VERDI, DVE

  • 01/2015 - 03/2016

    • MosChip Private Limited
  • Senior Engineer
  • Project: 3
    Project FPGA SOC Verification of Super strong LDPC/SanDisk LDPC algorithm

    client SanDisk India Device Design Centre, Bangalore
    Employer MosChip Private Limited, Bangalore
    Hardware Altera FPGA STRATIX IV, ARC Processor
    Role Senior Engineer
    Team Size 5
    Duration 4 months [ Oct'2015 to Mar'16]
    Description sLDPC decoder should be capable of detecting and correcting errors while making data retention often
    and should fail in decoding successfully a code word at the rate of once in 10-10 decoding cycles

    * Modified firmware to enhance testing features to measure performance.
    * Converted the Firmware to ELF, Debugged the firmware with SYNOPSYS ARC Processor
    * Validated the Superstrong LDPC algorithm/SanDisk LDPC algorithm for full data path Encoder,
    Scramblers, Noise Inserter with defined probabilistic behavior, decoder for Nand Flash model
    SLC, MLC =2,3

    Languages and Tools Verilog, C, Synopsys Metaware Debugger, Altera Insystem Memory Editor, Altera Quartus II

  • 03/2013 - 08/2015

    • Flowgic India Private Limited
  • Team Leader
  • Project: 4
    Project SOC Verification of NVMe compliant PCIe SSD Controller

    client Fastor Systems private Limited( Acquired by Smart Modular Technologies), USA
    Employer Flowgic India Private Limited, Chennai
    Hardware Xilinx FPGA Virtex5, Virtex7, Kintex 7;
    Processor Microblaze, PowerPC
    Boards Xilinx: ML509, KC705, VC709, custom: Tavanna
    Role Team Leader
    Team Size 7
    Duration 2.8 years[Mar'2013 to Aug'2015]
    Fastor's SSD is an innovative NVMe SSD based on a revolutionary network-oriented architecture.
    This will be the first "post-controller" SSD, in which the control and data planes are de-coupled
    and data congestion resulting from Flash controller bus contention is eliminated.


    Gate Level Simulation using Questasim
    * Worked on Gate Level simulation (Pre synthesis) and post layout simulation for
    equivalence checking and timing Verification
    Timing Closure
    * Worked on Static Timing Analysis in SOC level in VIRTEX 5 FPGA device: XC5VFX200T1738-2,
    * Used Chip Scope pro along with ILA for debugging
    * Used FPGA Editor with cross probing utility from PlanAhead for the timing violated path
    for the given constraints.
    * Created pblocks in PlanAhead for 3 Nand Flash Controller Octanes with 8 channels.
    * Did floorplan Optimization with locked pins for 3 Nand Flash Memory Controller Pins
    * Optimized DDR OLOGIC floor planning with respect to PPC440- X0Y0
    Bit File Generation
    * Worked on generating bit file for the developed Architecture, Tested with the XILINX API in
    SDK and validated it with U-Boot Linux with the Linux host pc, Evaluated the performance of
    SSD controller.

    Experience in PCIE PHY LAYER Verification using Lecroy Analyzer
    * Worked on PCIE PHY Layer, verified the PHY data in Chipscope and did double check in Lecroy

    Xilinx SDK Regression in XMD
    * Worked on creating and modifying scripts for Testing in XILINX SDK Software and Hardware

    Nand Flash Controller verification
    * Have explore in TCL script to test the read/write operation with multiple commands, super
    sequences for nand flash controller
    * Have explore in Perl scripts for block level Nand flash testing.
    * Developing test plan and Verilog/direct ,Developed C test cases to test Nand Flash (TOSHIBA
    toggle DDR1.0 )Basic, extended commands, with retry reads, with ECC enabled with different drive
    strength by excluding bad blocks in Questa simulation, XSDK, co-hardware and software simulation

    SOC with Dual PPC440 Processor
    * Solved the Booting issue for Dual processor XILINX IBM Power PC. Tested the Dual Processor
    Architecture by enhancing threads independently for Boot Loader, Embedded Hardware.
    * Developed shell script to run test case with different user options.
    * Assigning the bug on designer and follow up with bug tracker.

    SOC with Kintex, Vertex7 boards
    * Worked on developing the environment by Vivado tool using microblaze processor in Kintex KC705,
    Virtex 7 VC709
    * Generated the architecture for development
    * Generated User IP for AXI-PLB, PLB NVME
    * Integrated them in the developed environment
    * Analyzed the schematics for new environment

    Languages and Tools C, Verilog, perl, tcl, shell, make file, expect script, boot file, windows shell, Xilinx ISE 14.4,
    Vivado, Modelsim, Questasim,

  • 08/2012 - 11/2012

    • Quantenna Communications Inc
  • Team Member
  • Project: 5
    Project ASIC SOC Verification of BBIC4_L2 Switching controller

    Client Quantenna Communications Inc, Fremont USA from Flowgic India Private Limited
    Role Team Member
    Team Size 5
    Duration 5 months[Aug'2012 to Nov'2012]
    Description BBIC4- is a 4 Port switch, of them 2-Ethernet 1- Wi-Fi and 1 PCI-x ports, Which switches the Packets
    based on MAC address.

    * Worked as verification for Forwarding Table for Ethernet packet.
    * Written the comparison task when packet received in cpu.
    * Worked on testbench Component Update based on Verification features.
    * Developed test plan and test cases.