Profileimage by Massimiliano Giacometti Managing director at PlanV, from Parma

Massimiliano Giacometti

available

Last update: 15.05.2023

Managing director at PlanV,

Graduation: not provided
Hourly-/Daily rates: show
Languages: German (Limited professional) | English (Full Professional) | French (Limited professional) | Italian (Native or Bilingual) | Russian (Elementary)

Keywords

Field-Programmable Gate Array (FPGA) Verilog Workflows Python (Programming Language) Lithography Open Source Technology Simulations SystemC SystemVerilog Tcl (Programming Language) + 6 more keywords

Attachments

CV-giacometti_150523.pdf
cover-letter-freelance_150523.pdf
PlanV-intro_150523.pdf

Skills

FPGA and ASIC frontend design
RISC-V
open source hardware (GHDL, Icarus Verilog, Verilator, Vunit, Cocotb, Yosys, SiliconCompiler, Litex)
VHDL, Verilog, SystemVerilog, SystemC
FPGA workflows: Xilinx Vivado, Intel Quartus
RTL simulation: Modelsim, VCS, Xcelium
Synthesis: Design Compiler, Genus
C/C++
Workflow automation (tcl, Python)

 

Project history

06/2018 - 02/2022
Head of Hardware Development
HENSOLDT CYBER GmbH

HENSOLDT CYBER GmbH (Germany)
Responsible for the development of the MiG-V chip family: definition of the system
architecture, RTL design, integration of the components in the SoC, logic obfuscation,
definition and execution of the test strategy, definition and automation of the workflow,
FPGA prototyping, interfacing with EDA tool vendors, interfacing with backender,
interfacing with the SW team, interfacing with the University partners, recruiting,
mentoring new employees, reporting to CTO and Chief Scientist

05/2011 - 05/2018
Freelance consultant
INTEL MOBILE COMMUNICATIONS

INTEL MOBILE COMMUNICATIONS (Germany)
Development and verification of the FW and virtual prototype of a DMA: firmware
development in Forth, low level simulations with Synopsys VCS, design of the virtual
prototype in SystemC, interfacing with the HW development team, participating to the
chip bringup

08/2016 - 12/2017
Freelance consultant
INFINEON

INFINEON (Germany)
Development of the virtual prototype of smartcard chips (SystemC)

04/2015 - 11/2015
Freelance consultant
PHLUIDO

PHLUIDO (USA)
FFT HW acceleration based on Zynq and related Linux driver (Xilinx tcl and C)

03/2015 - 04/2015
Freelance consultant
MAVIGEX

MAVIGEX (Italy)
S-M2M modulator (C and VHDL)

06/2013 - 12/2013
Freelance consultant
MINDWAY

MINDWAY (Italy)
BCH + LDPC encoder development for DVB-T2 (VHDL code and C++ model)
Turbo encoder development for an FSIM modulator (VHDL code and C++ model)

01/2009 - 05/2011
FPGA Engineer
MINDWAY

MINDWAY (Italy)
RTL development and FPGA implementation of ECC systems ( ProMPEG-COP3, block
product codes) for broadcasting systems (VHDL and Xilinx Spartan3)

06/2010 - 11/2010
Freelance consultant
CNIT

CNIT (Italy)
Quantization and modeling (C) of a signal detection and synchronization algorithm for
satellite communications (C)

01/2008 - 12/2008
FPGA and FW consultant
INFO SOLUTION

INFO SOLUTION (Italy)
Optimization and FPGA porting of protection management for an optical multi-service
node
Development of an heating measurement system UNI EN 834 compliant (C and
assembly for Microchip PIC)

05/2007 - 11/2007
R&D engineer
TURBOCONCEPT

TURBOCONCEPT (France)
Design and verification of a low latency turbo encoder for Wimax (VHDL and Altera
Stratix2)

Local Availability

Only available for remote work

Other

I am an electronic engineer, with more than 15 years of experiece in ASIC and FPGA design&verification in several areas, from computer architectures to communication systems. In June 2022 I started PlanV GmbH, an engineering firm specialized in design and verification activities around FPGA and ASIC, with particular focus in RISC-V and open source hardware. Together with my team of talented engineers spread around the globe, we are keen on helping customers realizing their silicon dreams.
Profileimage by Massimiliano Giacometti Managing director at PlanV, from Parma Managing director at PlanV,
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