Upgrade Post project
YZ

Yaroslav Zazulyak

Ternopil
available

Last update: 24.05.2013

HW&SW engineer (Verilog/VHDL/Assembler/C++)

Company: Yaroslav
Graduation: not provided
Hourly-/Daily rates: show
Languages: English (Limited professional) | Russian (Native or Bilingual) | Ukrainian (Native or Bilingual)

Keywords

Skills

Programming Languages C/C++, Assembler for RISC;
Architecture CPLD, FPGA, RISC, ARM, SoC, DSP, OISC / URISC, PLC;
Interface RS-232c, SPI, I2C, 1-Wire, Ethernet(UDP);
Hardware Description Languages AHDL (Altera HDL), Verilog,VHDL;
PCB Design: Accel EDA PCAD 2000 /2002(for Windows), PCAD 4.5 (for MS-DOS), Altium;
Tools: Borland C++ 3.1, Max+plusII(Altera), Quartus II, Xilinx ISE Design Suite, ModelSim, , Matlab (Simulink), LabView, Multisim;
Platforms: Windows 95/98/XP/2000;
Debugging skills: oscilloscope, logic analyser.

Project history

INTERNET certificates:
UK ver.
http://www.intuit.ru/diplom/JeaGCqHmPBvt/A00156020/
http://www.intuit.ru/diplom/JeaGCqHmPBvt/A00155898/
http://www.intuit.ru/diplom/JeaGCqHmPBvt/A00155892/
http://www.intuit.ru/diplom/JeaGCqHmPBvt/A00155722/

Local Availability

Only available in these countries: Ukraine
8 hours per day.
Profileimage by Anonymous profile, HW&SW engineer (Verilog/VHDL/Assembler/C++) HW&SW engineer (Verilog/VHDL/Assembler/C++)
Register