Nejdaoui Abir available

Nejdaoui Abir

Senior design for test engineer

available
Profileimage by Nejdaoui Abir Senior design for test engineer from
  • Freelancer in
  • Graduation: Electronicengineer
  • Hourly-/Daily rates: not provided
  • Languages: Arabic (Native or Bilingual) | English (Limited professional) | French (Native or Bilingual)
  • Last update: 17.09.2016
KEYWORDS
SKILLS

• Test plan definition for Complex SOC modem. 
• Manufacturing test mode verification using vhdl test bench environment.
• Scan chain insertion using DFTMAX .
• Scan test mode verification using Tetramax tool of Synopsys.
• Scan pattern simulation using stildpv.
• Architecture & Design compensation cell Built In Self-Test engine in 65nm with vhdl.
• Functional verification of complex blocs: Digrf, DLL, PLL, DDR interface, JTAG.
• Memory bist test.
• Old life test patterns development.

REFERENCES

Work experience:

  • oct 2006 -august 2008: dft engineer at stmicroelectronics 

  • August 2008-july 2013 senior dft engineer at stericsson
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