JR

Jexter Reyes

available

Last update: 03.10.2017

IC Layout Engineer

Graduation: Bachelor Degree
Hourly-/Daily rates: show
Languages: English (Limited professional)

Attachments

jexter_reyes_cv.doc

Skills

A total of 15+ years of extensive experience in Full-custom Analog Layout for RFIC, PMIC, Mixed Signal, pure CMOS and Bi-CMOS design with 2+ years of experience as a Back-End/Physical Design Engineer. Have a portfolio of diversified and successful projects involved in a complex engineering design for 600nm down to 14nm FinFet technology process. Proactive, team player, multi-task with excellent problem solving skills that handle high pressure environments and meeting deadlines.

Project history

  • Taped out 16nm SRAM design
  • Taped out 20nm OTP design
  • Taped out 28nm SRAM design
  • Taped out 130nm OTP
  • Taped out multiple ECO layout activity in all USB 2.0

Local Availability

Only available in these countries: USA
Profileimage by Jexter Reyes IC Layout Engineer from Henrietta IC Layout Engineer
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