Profileimage by Danilyn Daculan Layout Engineer level2 from Tanza

Danilyn Daculan

available

Last update: 06.09.2022

Layout Engineer level2

Graduation: Electronics Engineering Technology
Hourly-/Daily rates: show
Languages: k. A.

Keywords

Attachments

cv_danilyn_daculan.pdf

Skills

  • Accomplished in physical verification, complex debug and problem solving skill for LVS, DRC, ERC and ANT using MENTOR CALIBRE and DRACULA layout verification tools.
  • Expert in using SX-Meister Layout Design tools by JEDAT (Japan EDA Technologies), Virtuoso XL by Cadence and Custom Compiler by Synopsys.
  • 4 years of experience in CMOS (planar) technology from 180nm to 90nm performing full custom layout for block and top block
  • Less than 1 year of experience in CMOS (finfet) technology from 7nm to 5nm performing full custom layout for block
  • Implementation skill in analog layout using matching techniques (symmetry structure, common centroid and orientation) and shielding (noise isolation/cross-talk).

Project history

01/2021 - Present
IC Layout Engineer level2
Xinyx Semiconductor Design Services Inc. (Other, 50-250 employees)

placement and routing of macro blocks from 5nm to 7nm
* Delivering Analog Layout blocks and top strategy
* Managing the power supply strategy and signal distribution between blocks
* Maintain and coordinates work schedules to ensure the objectives of cost, quality and
time are met.
* Create transistor level sub block layout based on schematics provided by Design/Circuit
Engineer.
* Implementing device matching, pairing, current mirrors and common centroid
placement.
* Guarantee compliance to technology design rule (DRC) and perform physical verification
(LVS).
*performce PERC verification
* Layout Analog Circuit

02/2017 - 01/2021
Junior Layout Technician 2
ROHM LSI Design Phil.; Ortigas Center (Other, 500-1000 employees)

* Delivering Analog Layout blocks and top strategy
* Managing the power supply strategy and signal distribution between blocks
* Maintain and coordinates work schedules to ensure the objectives of cost, quality and
time are met.
* Create transistor level sub block layout based on schematics provided by Design/Circuit
Engineer.
* Implementing device matching, pairing, current mirrors and common centroid
placement.
* Guarantee compliance to technology design rule (DRC) and perform physical verification
(LVS).
* Layout Analog Circuit
* Voltage Regulator (VREF/VREG)
* Thermal Shutdown (TSD)
* Oscillator (OSC)
* Bandgap
* Comparator (Comp)
* Current reference (IREF)
* ADC (Analog to Digital Converter)
* DAC (Digital to Analog Converter)
* AFE (Analog-Front-end)
* Operational Amplifier
* Phase-locked Loop

06/2016 - 12/2016
Material Quality Assurance - Lens Inspector Quality Assurance
M.UBIS Inc.; CEPZ

* Inspect Lens to ensure the product meets the safety and specification standards
necessity in production.
* Specialist ensures the final product observes the company quality standard.

Local Availability

Only available in these countries: Philippines
Profileimage by Danilyn Daculan Layout Engineer level2 from Tanza Layout Engineer level2
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