Profileimage by juturu venkatavijayakumar Senior layout engineer from

juturu venkata vijaya kumar

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Last update: 09.09.2022

Senior layout engineer

Graduation: Batchelors
Hourly-/Daily rates: show
Languages: English (Full Professional)

Attachments

vijaykumar_IO&Analog_8p6_Exp.pdf

Skills

LVS debugging, DRC, ERC, Totem (For Electro migration, Self-heat analysis, IR drop fixes, Synopsys, GPIO, HBM diode, driver, predriver, datapath, logic, rx, Clamp, PUPD, SDIO, HBM, PLL, Level shifter, DAC, CMOS, Antenna, Metal Density, Electro migration, IR drop, Latch-up, Shielding

Project history

10/2019 - 09/2022
Technical lead
Sevitech systems pvt ltd
40nm,28nm,7nm Project: (TSMC, UMC)
* Project's: IO PADS (TMIO,GPIO,P/G, ATB)
Designed all IO Pads from scratch including including the sub blocks like
HBM diode, driver, predriver, datapath, logic, rx, Clamp, Rcstage, PUPD,
CDM diode across 28nm UMC and 7nm TSMC technology nodes in multiple
Projects..
Job Responsibilities: - Top level Layout design, Verification, and IP Tapeout.
Abutment checks, Anteena checks, EMIR, PERC, LEF generation , physical
verifications(DRC/LVS).

12/2018 - 10/2019
Senior layout engineer
BlackPepper Technologies
40nm,28nm,7nm Project: (TSMC, UMC)
* Project's: IO PADS (TMIO,GPIO,P/G, ATB)
Designed all IO Pads from scratch including including the sub blocks like
HBM diode, driver, predriver, datapath, logic, rx, PUPD, CDM diode across
28nm UMC and 7nm TSMC technology nodes in multiple Projects..
Job Responsibilities: - Top level Layout design, Verification, and IP Tapeout.
Abutment checks, Anteena checks, EMIR, PERC, LEF generation , physical
verifications(DRC/LVS).

03/2018 - 12/2018
Senior layout engineer
Cerium systems pvt.ltd

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