Skills
I am a Goal-Oriented Senior Digital ASIC/FPGA Engineer with over ten years of experience. Several work experience enable me to pick up and own new concepts to contribute with innovative work. I have a Bachlor Degree in electronic since 2006.After worked in several big company, i have the qualification of engineering and engineering management experience in development or use of FPGA products, IP to complete a project.
Here is a list of my high level programming skills:
Verilog -- Reliable and efficient code for simulation and synthesis, mainly for Xilinx and Altera FPGAs. Also with experience in writing Verilog for ASIC. High awareness of device targetting in source code. Careful and secure clock domain crossings.
Perl/tcl/Make -- familiarity with the language,can write simple script to enhance the work efficiency
Circuit Board -- work closely with Hardware Design Engineer to discuss the system design.
Here is a list of my high level programming skills:
Verilog -- Reliable and efficient code for simulation and synthesis, mainly for Xilinx and Altera FPGAs. Also with experience in writing Verilog for ASIC. High awareness of device targetting in source code. Careful and secure clock domain crossings.
Perl/tcl/Make -- familiarity with the language,can write simple script to enhance the work efficiency
Circuit Board -- work closely with Hardware Design Engineer to discuss the system design.
Project history
IC front-end design engineer & Project Team Leader | KIWIMAGE Company
August 2016 - Present
1.Work closely with Project Manager to ensure resource workload balanced across projects.
2.Provide regular status reports for all activities related to the project.
3.Identify and resolve project issues,Identify and mitigate risks.
4.Compose some critical IP module: DSC (Display Stream Compression, a video compression standard proposal by VESA organization), AXI matrix bus,AXI to Local Bus converter,etc
5.Also take care of the Synthesis(using Synopsys DC ) and LEC(using Cadence LEC),post simulation work.
IC front-end design engineer | ZTE Corporation January 2010 - August 2016 1. Design a Intermediate Frequency chip's clock and reset system, and determine those relationship. This chip was successfully Taped Out.
2. Design the chip's architecture, and then break it down into block level.
3. Compose the main code of the Up Link, which were all verified and passed. Besides, these code were all organized by SVN.
4. Compose the code of the common library, and organized it. To use perl script to generate apb code from word document is a feature.
5. Establish the module level verification flow. Build the testbench (including BFM, ScoreBoard, etc ), using Verilog HDL. Further, use Perl script to enhance the efficiency.
6. Write the documents( like chip design document, etc).
7. Train the new employee.
FPGA Engineer and Hardware Design Engineer | HuaWei Technologies Co.Ltd. July 2006 - January 2010 1. Participate in the system's clock and reset plan.
2. Compose the code of IP packet flow control and frame header module, using Modelsim to simulate and then synthesis by Quartus.
3. Participate in the x86 board design, including schematic diagram check, board test and so on.
4. Know of the x86 CPU's application and its interface.
5. Receive LSI Corporation specialists.
2.Provide regular status reports for all activities related to the project.
3.Identify and resolve project issues,Identify and mitigate risks.
4.Compose some critical IP module: DSC (Display Stream Compression, a video compression standard proposal by VESA organization), AXI matrix bus,AXI to Local Bus converter,etc
5.Also take care of the Synthesis(using Synopsys DC ) and LEC(using Cadence LEC),post simulation work.
IC front-end design engineer | ZTE Corporation January 2010 - August 2016 1. Design a Intermediate Frequency chip's clock and reset system, and determine those relationship. This chip was successfully Taped Out.
2. Design the chip's architecture, and then break it down into block level.
3. Compose the main code of the Up Link, which were all verified and passed. Besides, these code were all organized by SVN.
4. Compose the code of the common library, and organized it. To use perl script to generate apb code from word document is a feature.
5. Establish the module level verification flow. Build the testbench (including BFM, ScoreBoard, etc ), using Verilog HDL. Further, use Perl script to enhance the efficiency.
6. Write the documents( like chip design document, etc).
7. Train the new employee.
FPGA Engineer and Hardware Design Engineer | HuaWei Technologies Co.Ltd. July 2006 - January 2010 1. Participate in the system's clock and reset plan.
2. Compose the code of IP packet flow control and frame header module, using Modelsim to simulate and then synthesis by Quartus.
3. Participate in the x86 board design, including schematic diagram check, board test and so on.
4. Know of the x86 CPU's application and its interface.
5. Receive LSI Corporation specialists.
Local Availability
Only available in these countries:
China
