SL

shahbaaz lokhandwala

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Last update: 09.11.2022

Senior FPGA Design Engineer

Graduation: B.Tech Electronics and Communication
Hourly-/Daily rates: show
Languages: English (Full Professional)

Attachments

shahbaaz_detailed_updated_resume.pdf

Skills

  • Hardware Implementation of SHA3-256 hash algorithm in Verilog on Xilinx Ultrascale+ fpga VCU1525 Acceleration Development kit for mining SmartCash coin(cryptocurrency).
  • Hardware Implementation of SHA2-256 hash algorithm in Verilog on Xilinx Ultrascale+ fpga VCU1525 Acceleration Development kit for mining Bitcoin (cryptocurrency).
  • Hardware Implementation of keccak800 hash algorithm in Verilog on Xilinx Ultrascale+ fpga VCU1525 Acceleration Development kit for mining Odocrypt coin(cryptocurrency).
  • Hardware Implementation of Eaglesong hash algorithm in Verilog on Xilinx Ultrascale+ fpga VCU1525 Acceleration Development kit for mining Nervous (CKB)coin(cryptocurrency).
  • Hardware Implementation of Ethash hash algorithm in Verilog on Xilinx Ultrascale+ fpga VCU1525 Acceleration Development kit for mining Ethereum coin(cryptocurrency).
  • Hardware Implementation of Ethash hash algorithm in Verilog on Xilinx Ultrascale+ fpga xcvu33p-fsvh2104 with HBM for mining Ethereum coin (cryptocurrency).
  • Hardware Implementation of OFDM transmitter and OFDM receiver on Digilent zybo z7-20 fpga development board using MATLAB Simulink and HDL code generator.
  • Implementation of HDMI PHY on artix-7 fpga for custom video processing fpga board for commercial use.
  • Working closely with PCB hardware design team for designing custom board. Developing roadmap for custom board bring up as per specification.
  • Developing projects to verify all bus interface are working with IIC, SPI, UART, HDMI, DDR3 etc. with microblaze soft-processor for custom board.
  • Designing micro-architecture of algorithms on fpga. Implementing hash algorithm with fully-unrolled and pipelined architecture to achieve maximum throughput and fabric clock frequency ranging from 300MHz to 550MHz.
  • Handling Cross-Clock Domain and STA analysis on failing nets, familiar with synthesis and implementation constraints. Designing block level design (IPI design) using Xilinx Vivado software tool.
  • Developing custom IPs in Verilog with AMBA AXI4 protocol such as AXI4 stream(master/slave), AXI4-lite(slave), AXI4(master) to communicate to other IP’s.
  • Developing custom IPs in c/c++ using Xilinx Vitis hls software with AMBA AXI4 protocol such as AXI4 stream(master/slave), AXI4-lite(slave), AXI4(master) to communicate to other IP’s.
  • Developing tcl script for design automation from creating Vivado project to bitstream. Implementation of PCIe interface using xdma_pcie ip from Xilinx for sending and receiving data from host to card and card to host on fpga that supports PCIe bus.
  • Familiar with design and implementation of on Chip HBM(Highbandwith memory) and off Chip DDR3/DDR4 external memory interface.
  • Developing host software multithreaded application in python to communicate to server and FPGA.
  • Writing technical content for the projects developed on company website and other third-party websites for digital marketing and SEO.
  • Planning and development of projects from RFQ’s.

Project history

Designation: FPGA Application Engineer .
Company: Eleics Design Pvt Ltd.
Website:- www.eleics.com
Product :- 16 – Channel Nano-Voltmeter.
Duration: 16/08/2017 to present.
Responsibilities:

- RTL Design of SPI and UART to interface ADC with Spartan-6 Fpga.
- Design of system architecture for Data Accuisition from ADC .
- Block level Design in Vivado.
- Developing Application using SDK.
- Building Application with Petalinux.
- Analog front end design.


Designation: Design Engineer
Company: Global Tech India Pvt Ltd.
Website:- www.thegt.com
Product:- CNC Router.
Duration: 1/02/2015 to 14/04/2017.
Responsibilities:

- Designing of overall project Architecture according to specification.
- Interface FPGA with FX2LP Microcontroller for Data Accusition.
- Verilog Code for Motion Control as per Commands from user interface.
- interface USB Pendrive to send G-code file to FPGA.
- Load bit-file to FPGA.

Local Availability

Only available in these countries: India
Profileimage by shahbaaz lokhandwala Senior FPGA Design Engineer from Senior FPGA Design Engineer
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