Analog layout designer

Experience in Professional Analog Integrated Circuit and Layout Designs. Mixed Signal Circuit design of High Power and High Performance Analog devices for Audio Products. Familiar with Integrated Class-D audio Amplifiers and Audio DSP (Digital Signal Processing). Succeeded in outstanding design new products development, modification and system evaluation for Integrated Circuitry, components or parts of Electronic Equipment and Hardware system.

Specialties:
• Design Sync, Cadence Open Access, Cadence Virtuoso-XL, Cadence Assura, Place & Route tool.
• DRC (Design Rules Check) and LVS (Layout Versus Schematic), ERC (Electrical Rules Check) Verification, K2 Chameleon VER, DIVA and Cadence Assura.
• ARC (Assembly Rules Check), Power Plots, CLEO (ESD Latch-up), Antenna Rules Check, PG (Patten Generation).
• UNIX, Linux, Windows, Microsoft Word, Power Point, Excel.

• Responsible for developing New Products on the Low Power Devices, RTC (Real-Time Clock), LDO (Low-Drop Out), VREFBUF, IBIAS, Voltage Band Gap, REFSYS (Reference System Elements) TOP layout floor plan. Charger REF Design, DECODER, Charge Driver, HSFET and LSFET, ESD padring and Flip Chip design. PWM (Pulse Width Modulator), PLL (Phase Locked Loop), CP (Charge Pump), Power Amplifier, Op-amp, Bias, Delay cells, VCO (Voltage Control Oscillator), Common Mode, Power Fets devices.
• Improvements resulted in reduction of product size.
• Implemented physical layout of analog circuit blocks using critical devices matching, noise isolation guard ring, shielding layers, sensitive components, symmetrical devices, common centroid, cross couple, interdigitate, dummy fill generation for submicron devices.
• Accomplished many high level projects from the beginning to the end.
• 1833C05 process, LBC5 (Linear Bipolar CMOS) process, LBC7 and LBC8LV process design rules.