Profileimage by Rudolf Usselmann Freelancer, ASIC/FPGA Design from Chonburi

Rudolf Usselmann

available

Last update: 06.09.2022

Freelancer, ASIC/FPGA Design

Graduation: Computer Science
Hourly-/Daily rates: show
Languages: German (Native or Bilingual) | English (Full Professional)

Keywords

Attachments

resume_latest_int.pdf

Skills

Over 25 years of hands on design and development experience with emphasis in custom IC and FPGA design. Excellent Verilog HDL design, verification and synthesis skills. Broad background, proven track record. Highly motivated, excellent project management skills.

Project history

03/1999 - 05/2020
Consultant
Synopsys Inc.

* Gave a 3 day VERA training course to a group of 20 potential clients in Tokyo, Japan
* Provided VERA pre-sales tech support in Tokyo, Japan

01/2001 - 05/2002
Consultant
Flextronics

* Developed various IP Cores. These cores included: USB 2.0, advanced memory
Controller, DMA Engine, AC97 Controller and WISHBONE Connection Matrix. These
cores where donated to OpenCores.org and are now freely available for download

09/1999 - 12/2000
Consultant
Teryx Inc.

* Responsible for the overall hardware system architecture of a small telephone switch
* Designed several system blocks for FPGA implementation and later porting in to ASICS.
These included a Traffic Controller Chip, system interface chip and expansion module
interface chip

01/2000 - 03/2000
Consultant
Synopsys Inc.

* Writing Application Notes and provide Technical Support to users of Synopsys VERA
verification tool

09/1998 - 01/1999
Consultant
Synopsys Inc.

* Provided technical support to VERA users
* Wrote application notes, and methodology examples
* Provided VERA pre-sales tech support in Tokyo, Japan

07/1997 - 12/1998
Consultant
Sun Microsystems

* Wrote Ethernet packet generator and checker, capable of Level 2 and Level 3 packets
utilizing G/MII interface at 100/1000 Mbs




* Wrote complex verification environment for a multi-port switch chip

08/1997 - 11/1997
Consultant
3Com Corp.

* Developed complex cable router head-end model compliant to MCNS specification in
Verilog
* Integrated DES encryption engine written in C into Verilog XL, using PLI interface

12/1996 - 07/1997
Consultant
CISCO Systems Inc.

* Developed complex cable router and cable modem model compliant to MCNS
specification
* Wrote stress tests to verify a cable router with many subscribers

07/1996 - 12/1996
Consultant
3Com Corp.

* Setup test environment for system level testing on a new bridge ASIC between PCI and
ISA bus for a new Tokenring board
* Wrote library functions to manage upload and download data path, traffic generation, and
final verification
* Wrote actual tests to perform functional verification and stress testing

08/1996 - 11/1996
Consultant
Synopsys Inc.

* Develop test designs to verify Arkos emulation / simulation engine, assisted in debugging
the new software/hardware solution
* Improved manufacturing vectors to get higher yield

03/1996 - 07/1996
Consultant
CISCO Systems Inc.

* Responsible for setting up environment to stress test a switch
* Wrote several behavioral models to verify a new 10/100Base-T switch used Chronologic
Verilog to verify models

10/1995 - 05/1996
Consultant
Synopsys Inc.

* Designed a small 130K gate ASIC containing wide data and pipelined control path
* Synthesized design using Design Compiler, verified timing with back annotated layout
delays
* Developed fault detection test vectors for a 3M gate ASIC
* Wrote fault vector generator and ASIC model in C to predict behavior

10/1995 - 01/1996
Consultant
Adaptec Inc.

* Set up system simulation for "fire wire" (P1394) host adapter talking to PCI bus
* Developed test suite to verify device driver with host adapter

05/1995 - 10/1995
Consultant
Adaptec Inc.

* Set up system simulation environment including Verilog PLI interface to actual
production device drivers written in C
* Wrote tests to verify new SCSI host adapters backwards compatibility with existing
device drivers
* Developed test suite to check new drivers with the new SCSI host adapter
* Developed test suite to verify PCI bus interface

06/1994 - 08/1995
Consultant
Tandem Computers

* Developed chip and system level test suites for ATM network interface controller
containing a 68060, 68336 a custom Gate Array and a NEC ATM chip set
* Wrote numerous Verilog models for accelerated chip verification (including 68060 bus
model, PCI bus model, TNet model)
* Designed a chip level validation environment including over 200,000 test cases
providing over 95% test coverage after first pass run
* Assisted junior designers with HDL coding and synthesis

01/1994 - 04/1994
Consultant
Phillips Semiconductor

* Provided tools support for 20 design engineers
* Installed, backed-up and maintain Cadence design environment, Synopsys tools
* Assisted with trouble shooting, built custom Verilog executable

02/1989 - 12/1990
Chief architect
Lattice Semiconductor Corp.

* Presented to the CEO new device ideas to help establish company's future direction
* Received two device architecture specific patents
* Responsibilities included: market studies; customer interviews; architecture definition;
visibility studies and design

05/1988 - 12/1988
Consultant
LSI Logic Corp.

* Led design team to develop next generation MBus & SBus chip-set
* Defined architecture of several chips for the SPARCkit
* Responsibilities included: defining architectures; hands on design; single and multi chip
(system) simulation and verification; writing reports and preliminary
manuals/specification

03/1987 - 05/1988
Consultant
Sun Microsystems

* Worked with engineering team to define SBus
* Designed major logic blocks in multiple ASICs
* Tapped out "Buffer" and "Video" ASICs
* Brought up the first full multi-chip simulation of SPARCstation 1
* Developed and ran test vectors on system mode, discovered numerous bugs
* Worked with Weitek on their new multi interface FPU for SUN (Bonfire)
* Responsibilities included: defining and designing ASIC's, new system architectures
(SPARCstation 1) and buses (SBus & MBus)

06/1983 - 12/1986
Principal of Usselmann Computer Systems

* Developed systems for the ECB (Euro Card) and VME Bus
* Designed custom-specific hardware and software
* Wrote BIOS for CPM 3.0 for custom designed Hardware. This included special memory
management, communications, floppy and SCSI drivers. Performed complete porting to
the new hardware
* Tasks included: prototyping, debugging, pre-production release and documentation
* System examples: intelligent high resolution graphic terminal, mass storage controller to
manage hard disks, streamers and floppies

Local Availability

Only available in these countries: Austria
Currently, I live in Thailand, but do not mind relocating or traveling.
Profileimage by Rudolf Usselmann Freelancer, ASIC/FPGA Design from Chonburi Freelancer, ASIC/FPGA Design
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