SB

Stephan Berner

available

Last update: 27.02.2013

DSP engineer

Company: SBE Engineering EOOD
Graduation: PhD
Hourly-/Daily rates: show
Languages: German (Native or Bilingual) | English (Full Professional) | Spanish (Limited professional)

Keywords

Field-Programmable Gate Array (FPGA) Prototyping C++ (Programming Language) Linux MATLAB Simulations Simulink C (Programming Language) Algorithm Design Printed Circuit Board + 17 more keywords

Skills

Expert (PhD) in communications and DSP. Experience in physical layer design, algorithm design, simulation and FPGA prototyping. Experience in electronic design and programming.

Matlab, Simulink, C, C++, ASIC, FPGA, DSP, VHDL, Verilog, Clear Case, Linux, QT3, Xilinx, Lattice, Altera, TI, Microcontroller, PCB design, Protel, embedded, Atmel, Microchip, Modelsim, radar, industrial control, video, image processing, prototyping,

Project history

8/2012 - 02/2013: A famous Swedish Camera Manufacturer, Gothenburg, Sweden
(NDA does not allow disclosure of company name)
Image processing and JPEG encoding for high end cameras, FPGA implementation.

8/2011 - 7/2012: Ericsson, Gothenburg, Sweden
ASIC design for Digital Predistortion (DPD), Architecture design, Matlab/Simulink simulation, VHDL coding, Verification
Tools used: Matlab/Simulink, Modelsim, Clear case (Unix),
Algorithm Experience: Delay compensation, adaptive algorithms, LMS loop, modeling of nonlinearities,

8/2010 - 7/2011: Alcatel-Lucent, Stuttgart, Germany
DSP implementation of VAMOS algorithms (VAMOS is a MIMO based GSM enhancement for capacity increase), simulation, writing highly optimized C code for TI C64xx DSP
Tools used: Matlab, TI code composer
Algorithm Experience: MIMO, channel estimation, DFE, MAP detection

5/2010 - 8/2010: Lake Communications, Dublin, Ireland
FPGA design for phone systems, high speed backplane communications, complex state machines
Tools used: VHDL, Verilog, Modelsim, Xilinx ISE, Spartan
Algorithm Experience:

5/2009 - 1/2010: GCM, Madrid, Spain, www.gcmcom.com
Design of a modem based on GCM's proprietary technology. I was involved mostly with carrier and frame synchronization, doing research, Matlab simulation, VHDL coding, Modelsim simulation, FPGA prototyping.
Tools used: Matlab/Simulink, VHDL, Modelsim, Xilinx ISE, Virtex 4
Algorithm Experience: carrier synchronization loops, filter design, frame synchronization at low SNR,

6/2003 - 5/2009: ESI, Los Angeles, CA, USA
Electronic system design from concept up to working prototype, various projects from different areas for different customers. Was involved in all stages of the project, architecture, simulation, component selection, circuit design analog and digital, PCB design, assembly and testing, programming.
Projects and tools used:
1) Kalman filter implementation for UAV navigation system: Matlab/Simulink
2) Real time video rotation: Matlab, Xilinx ISE, Spartan 2, VHDL, Protel
3) Servo control over ethernet: Linux, QT3, MCU (80186 based, type=?), C, Protel
4) Radar gun: Microwave office, Matlab, Protel, Atmel MCU, C
5) Flight computer for UAV: Protel, Linux, gcc, Atmel MCU, C
6) Document scanner: Matlab, Protel, Altera Quartus 2, Stratix 2, VHDL, NIOS 2 CPU core, C
7) Servo control over RS485: Protel, Microchip MCU, C
8) Numerous other microcontroller projects, mostly industrial control: always Protel, Atmel or Microchip MCU, C
Algorithm Experience: Kalman filter, image rotation and interpolation, image compression, radar doppler detection with FFT, control loops

6/2001 - 5/2002: Valence Semiconductor, Calab., CA, USA
Prototyping of wireless networking devices (802.11a physical layer) in FPGAs. My tasks were implementation of 802.11a PHY in Verilog (starting from floating point simulation provided by other engineer), testing in Xilinx evaluation board, interfacing to PC (ISA bus, MS-DOS), performance evaluation
Laid off after company (start up company) went out of business
Tools used: Matlab/Simulink, Verilog, Modelsim, Xilinx ISE, Virtex 2
Algorithm Experience: all of 802.11a PHY, OFDM (pipeline FFT/IFFT), carrier synchronization, equalization,

1/1998 - 5/2001: New Mexico State University, Las Cruces, NM, USA
Research Assistant, work on parallel signal processing (multirate processing) based on filterbanks, theory and FPGA prototyping
Tools used: Matlab, VHDL, Modelsim, Xilinx ISE, XC4000, wire wrap protoyping, Motorola DSP (type=?)
Algorithm Experience: see publications

8/1995 - 12/1997: Hope Electronics, Seoul, Korea
Design of radar systems, architecture, hardware, firmware. Task was to build a system (radar scan converter) to interface to radar set (video, ACP, ARP), digitize radar video and transmit it to remote sites.
Quit to study for PhD
Tools used: MS-DOS, MASM, Borland C, AMD PLD software, prototyping, 40486
Algorithm Experience: antenna synchronization with resolver, radar signal analog preprocessing, CFAR, m-of-n detection, sea clutter

Local Availability

Open to travel worldwide
May/2013, Europe

Other

EDUCATION:

1/1998 - 5/2001: New Mexico State University, Las Cruces, NM 88003
PhD Electrical Engineering in Communications and Digital Signal Processing

9/1990 - 6/1993: Ruhr Universitaet Bochum, Bochum, Germany
Dipl. Ing Elektrotechnik, Electronics

9/1987 - 9/1990: Fachhochschule Bochum, Germany
Dipl. Ing (FH) Elektrotechnik, Power


PUBLICATIONS:

S. Berner and P. De Leon, "Subband Transforms for Adaptive, RLS Direct Sequence Spread Spectrum Receivers," IEEE Trans. Signal Processing, Volume 53, Number 10,
pp. 3773 - 3779, Oct. 2005.

S. Berner and P. De Leon, "Subband Transforms for Adaptive Direct Sequence Spread Spectrum Receivers," 35th Asilomar Conference on Signals, Systems and Computers
(Pacific Grove, CA.), 2001.

S. Berner and P. De Leon, "Parallel Digital Architectures for High-Speed Adaptive DSSS Receivers," 34th Asilomar Conference on Signals, Systems and Computers
(Pacific Grove, CA.), 2000.

S. Berner and P. L. De Leon, "FPGA-Based Filterbank Implementation for Parallel Digital Signal Processing," 8th NASA Symposium on VLSI Design (Albuquerque, NM.),
1999.
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