20 Freelancers
ASIC RTL Principal Digital Designer
Davide Lequile
Senior FPGA Design Engineer
shahbaaz lokhandwala
Embedded Engineer
Sri Panda
Senior engineer
Sivasubramanian Manickam
Computer Engineer
Mykola Voloshyn
Digital IC Design & Verification
Fredy Morales
ICT/Electronic Engineer
Sciaraffa
Research Scientist
Keyur Mahant
RTL Design Engineer
Sachin Munji
FPGA Design DSP Verilog VHDL Matlab consultant
Eugenio Salazar-Brenes
Embedded Software Engineer
Adrian Popa
Design and Verification Engineer
Mahmoud Maher