Description
We are looking for an
Expert in the area of Layout Verification (m/f)
Reference: -en
Start: asap
Duration: 4 MM++
Place: in München
Branch: Herstellung von sonstigen elektronischen Bauelementen
Your tasks:
- Implementation and verification of PERC rule sets
- Review potential ESD errors in CMOS technologies
Your qualifications
- Profound knowledge of layout verification
- Experience with Mentor PERC
- Ideally experience with ESD
Skills:
- Hardware developer
Keywords: PERC ERC Electrical Rule Check Verification ESD