Staff/Principal FPGA Verification Engineer

Description

• Staff/Principal Level FPGA Verification engineer will be working in the hardware team.
• Strong experience with System Verilog and Synopsys UVM would be a key advantage.
• Developing self-checking test benches will be important, and the ability to work well with the design team.
• Ability to write scripts and work in a Clearcase revision controlled environment is also important.
• Will work with FPGA design engineers primarily but also across other sites as needed.

• Experienced in System Verilog & UVM
• UVM and SystemVerilog combination is ideal, would also look at Verilog or VHDL experience.
• Manager prefers Synopsis experience in particular, but will also look at Mentor/Questa/Cadence.
• Someone who comes from Telecommunication company would be ideal fit.
• Track record of self-checking complex FPGA (or ASIC) verification test benches
• Experience with Synopsys VCS or Mentor Questa tools
• 5-10+ years' experience
• Communication standards and protocols (Ethernet, Interlaken, PCIE)
• Scripting (Shell, Perl)
• Computer Science or Electronic Engineering Degree
• 5-10+ years' experience
• Previous experience in Verification test benches
• Ability to demonstrate FGVH6/hands on experience
• Ability to write scripts
• C/C+/revision control
• Communication standards and protocols (Ethernet, Interlaken, PCIE)

• Computer Science or Electronic Engineering Master's Degree (Advantage)
• Use of Synopsys VIP also an advantage
• Embedded systems, telecommunications and/or cable communications knowledge an advantage.
• UVM experience
• Soft Skills: Works well with FPGA Design and Hardware board designers. Also ready to help software engineers in bringing up FPGA design in the lab.