Description
FPGA Designer (DSP implementation)
Spain or Fleet, UK
Contract
EUR/day
The Company
A leading semiconductor customer
The Role
The R&D Physical Layer FPGA FW Engineer will be responsible for the design and implementation of VHDL based physical layer modems for 5G wireless communications standards.
The Individual
- 8 years minimum of relevant experience with typically 10-12 years.
- Experience with architecture, design, verification and debug of RTL (VHDL/Verilog) targeted for FPGA and/or ASIC, including debug in RTL simulation or lab environment.
- Experience with architecture, design and implementation of the physical layer of one or more of the following wireless communication standards: 5GNR, 5GTF, LTE, Cat-M1, NB-IoT.
- Experience with simulation and modelling of digital communications systems, using Matlab, Simulink, Python, C/C++ or other simulation and modelling languages and tools.
- Advanced understanding of Digital Signal Processing and RF concepts
ConSol Partners
We are a leading consultancy in the niche IT sector. We work with companies ranging from small start-ups to multinational conglomerates on both permanent and freelance positions.
ConSol Partners focus only on niche markets to give unrivalled access to our extensive network of highly skilled candidates so we can delivery only the highest quality to our clients.
Founded in 2008, ConSol Partners are one of the world's leading technology recruitment brands with headquarters in the City of London and international offices in Los Angeles & Boston. ConSol Partners provide permanent and contract recruitment solutions to FTSE & Fortune 500 companies, global brands and start-ups across the Internet supply chain of Communications, Cloud and Digital.