Design Verification Engineer

Graz  ‐ Onsite
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Description

Our client based in Austria, Graz are seeking an engineer to join their verification team.

You will be responsible for verification of RTL at block and SOC level.

Debug and maintain test code to meet exact standards.

60% Remote after an initial period of 2 months on site

Skills/Experience -

Experience working with Hardware design

RTL - Verligo/SystemVerilog/VHDL

OOD - Experience with writing code in embedded C/Java would be a bonus.

Experience in the use of EDA tools for IC development, simulation and debug

Many thanks,

Michael
Start date
01/2020
Duration
12 Months
From
Source Technology Ltd.
Published at
18.12.2019
Project ID:
1864055
Contract type
Freelance
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