Description
- Verification Engineer - SystemVerilog/UVM
- £500 per day - Inside IR35 - this rate is negotiable for the right person
- 6 month initial contract but very likely to extend for up to 2 years
- A mix of home working and attending the offices in Cambridge 1-2 times per week
Working for a global Software Design company we require an experienced and highly motivated Verification Engineer to join a fast growing team and verify our next generation of state of the art GPUs. The team predominantly employs constrained-random coverage-driven simulation techniques using SystemVerilog and UVM.
You will play a key role in the team - both with hands-on project work, creating and deploying new methodologies within the team.
About the team:
Working in our main office, located in Cambridge within a team that spans three sites across Europe. The team includes design, verification and modelling engineers working on the next gen graphics processors. Given the span of the team, there may be opportunity for travel to other sites during your work.
What will you be accountable for?
The role covers development and deployment of methodologies as well as direct hands-on test bench development.
You will be responsible for:
- Reviewing and assessing proposed design changes Architecting verification IP and full verification environments. You are expected to investigate and script new verification flows and optimising existing flows Developing methodology and deploying within the group and having full ownership of verification closure.
What skills, experience and qualifications do I need?
- You will require a proven track record with constrained-random verification including ownership of a suitably complex verification environment.
- Be comfortable using SystemVerilog to develop verification components and be familiar with the tools and processes for developing test benches and finishing all aspects of the verification process.
- You are capable of developing verification flows to make best use of EDA tools.
- Strong experience with SystemVerilog for verification of complex design IP.
- Experience of architecting and implementing functional verification environments for complex IP.
- Experience developing re-usable and scalable code whilst having good knowledge of UVM.
- Strong Scripting skills (UNIX Shell Scripting, Python or Perl) - being able to develop Scripting to support new flows.
- You possess the ability to quickly understand and apply complex specification details and capable of owning all stages of a project to completion.
- Willingness to tackle varied and complex technical challenges.
- Strong communication skills and ability to work well as part of a team as well as experience working and communicating with remote design centres.
Knowledge of graphics principles. Knowledge of C/C++, Scala/Java and good software principles. Experience with formal verification. Experience with emulation flows.