Description
We are looking for a
Functional verification engineer with system Verilog UVM (m/f)
Reference: -en
Start: asap
Duration: 3 MM++
Place: in Bavaria
Branch: Herstellung von sonstigen elektronischen Bauelementen
Your tasks:
- Chiplevel verification
- Mixed signal and digital verification with UVM
Your qualifications
- Experience in the semiconductor industry
- Very good knowledge with system Verilog
- Good expertise with UVM
- Experience with mixed signal verification and simulations
- Very good command of English
Skills:
- Hardware developer