Description
System modelling (C++) Contract Shannon 6-12 Months.
My client a leading light in the IT space is in urgent need of an experienced System modeller (Developer) to join them on a contract basis of 6-12 months.
You primary Skills, will be RTL, C/C++/SystemC, Modeling, Verilog. You will be required to model validation of a new piece of IP that is in planning. The modelling will be C/C++/SysC based using an internal proprietary tool. You will have to be able to come up to speed pretty quickly so experience in RTL/uArch design is required. Familiarity with IP Networking concepts & flow based routing is also desired. A big part of the job will be in constructing stimulus patterns to validate the model. All validation will be performed using the internal tool. This may involve creating custom reports and analyses.
You will have an 8 years of commercial experience in Front End (RTL) design & micro-arch, you will also have High speed (400MHz +) experience. You will have knowledge of System C, C++ this is essential.
This is a great role working with a global blue chip firm, if it sounds of interest drop me a CV so we can discuss.