UVM, Verification ( We can provide sponsorship if you require i

London  ‐ Onsite
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Description

Proteus Europe is currently searching for an UVM Verification Engineer for one of our clients an the verification of their world leading Image Signal Processor (ISP) IP cores. This role is critical to quality, in delivering synthesizable IP cores to multiple SoC manufacturers serving the camera and mobile devices markets. A wide breadth of experience in verification methodologies is essential, as they will play a critical role in driving our clients verification processes.

Skills Required:
- Good knowledge of verification methodologies - excellent UVM is critical
- VHDL, Verilog and System Verilog
- Low power design techniques
- Perl, Python, tcl
- Understanding of hardware design, demonstrated by experience in the field
- Tools knowledge - VCS, Cadence NC, Atrenta Spyglass, Modelsim
- Minimum first degree at 2:1 or above in a relevant technical subject.

Desirable skills:
- Debug experience
- FPGA, Synopsys DC and C, C++
- Assertion based verification
- Formal verification

Experience Required:

- Previous experience of system level verification in a commercial development environment is essential.
- The successful candidate will be able to demonstrate having produced or contributed to customer facing verification reports.
- Previous experience working in a hardware design function before moving into verification is required

Other Requirements:

- The candidate must be highly motivated, keen to make a real contribution to our clients range of IP and development processes.
- Good communication is essential as they will be working very closely with the hardware team and algorithm engineers.

For the first step in the recruitment process, please get in touch with me and I will chat with you in more detail about this role and the next stage of the recruitment process. I look forward to hearing from you.
Start date
10/2015
From
Proteus Europe
Published at
08.10.2015
Project ID:
997526
Contract type
Permanent
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