Senior Digital Verification Engineer

NL  ‐ Onsite
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Description

Senior Digital Verification Engineer

I am currently looking for a Senior Digital Verification Engineer to be based in Netherlands.

Main responsibilities:

  • Block level verification
  • Front End RTL design of digital circuits
  • Basic synthesis and timing verification
  • Documentation of the work done
  • Written and verbal communication

Expected Skills

  • M.Sc./BSc. in electronic engineering or equivalent.
  • 5+ years experience in digital IP level verification.
  • Decent knowledge of Verilog and/or VHDL design languages
  • Experience with Verilog-AMS
  • Experience with Cadence design environment
  • Able to identify and resolve complex issues.
  • Good communication skills (verbal and written), team player, driver mentality, pro-active attitude.
  • Networking skills, creative, motivating, curious, open minded.
  • Fluent English speaker.

Please send an updated CV to apply!

Start date
ASAP
Duration
8 months
From
Tangent International
Published at
29.06.2016
Project ID:
1156984
Contract type
Freelance
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