Description
Two openings in Raleigh, NC! Full time 2 year contract positions! Develop IC Custom layout of SRAM arrays in TSMC and IBM process including bit cells, columns, clock circuits, and control logic using Cadence 6.1 Tool Suite. Library cell development of LCBs, latches, receivers, and array cells. Verification using Mentor Graphics Calibre.
Minimum Qualifications:
5+ years layout experience. Tool experience using Cadence Virtuoso 6.1*, VXL, Calibre verification (DRC, LVS, ERC). Able to independently perform efficient debugging of verification results and implement timely layout corrections. Efficient management of engineering change orders.
Preferred Qualifications:
Perform UNIX directory management. LEF/DEF familiarity. Finfet technology experience desired Automation experience a plus.
Education:
Required: Associate's, Electrical Engineering or Computer Engineering
Preferred: Bachelor's, Electrical Engineering or equivalent experience