Description
Smartedge's client is looking for a " VHDL FPGA Design Engineer & Verification engineer"
Job description:
- Duration: 12 months
- Start Date: ASAP
Main day to day duties:
- VHDL Development
- FPGA Design/Documentation
- Code conversion
- Graphic Development
Key Skills and competencies
Essential:
FPGA
VHDL
Design/Documentation
Requirements
Desirable:
Knowledge of video standards
Aerospace background preferred but not essential
We have been asked to schedule the discussions this week, please share your updated CV and call for confidential chat.