Description
ASIC, "block verification", Apriso, "Verification IP", VHDL, SystemVerilogWe are looking for Senior ASIC block verification Consultant for a contract role to start ASAP in Kista, Sweden
The Senior ASIC block verification consultant will be part of digital radio ASIC products (mainly for signal processing and high speed interfaces) in SystemVerilog/UVM environment.
Do you have the competences needed and will you be available shortly? If yes could you forward your latest CV in Word format and a contact number for us to speak
Competence requirements
- Very good skills in understanding spoken/written English, as well as speaking and writing in English
- Capable of creating good working relations and networks with the Customer personnel
- Ability to work under the circumstances that the specifications are developed in parallel with the development, i.e. everything is not defined when the work starts
- Preferably min 5-7 years of advanced ASIC verification
- Verification environment architecture definition
- Development of verification plan (Vplan)
- Extensive knowledge in VHDL and Verilog
- Good VIP (Verification IP) design knowledge
- Good SystemVerilog assertions knowledge
- Analysis of code coverage
- Managing and debugging regressions
- Evaluate regressions and mapping to Vplan
Nice to have
- At least 1 Apriso MES implementations experience.
- Experience on Apriso Testing, with end to end testing MES Scenarios, from SAP ECC -MES to MES-Shop Floor Machine Integrations
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