Description
Our market leading client is a leading telecom solutions provider. Through continuous customer-centric innovation, they have established end-to-end advantages in Telecom Network Infrastructure, Application & Software, Professional Services and Devices. With comprehensive strengths in Wireline, wireless and IP technologies, they have gained a leading position in the All-IP convergence age. Its products and solutions have been deployed in over 100 countries and have served 45 of the world's top 50 telecom operators, as well as one third of the world's population.
They develop next generation RF transceivers, front-ends and peripheral circuits, supporting 2G, 3G and 4G (LTE) protocols. In our advanced R&D team, they are also pioneering the next generation 5G cellular chipsets. Today, they're seeking a RF IC layout expert who get things done and shares a passion for bringing new wireless technologies to the rapidly growing mobile market. Now is your chance to join the team and to develop new, world-leading products.
Job DescriptionWe are offering a senior layout engineer position enabling you to join the creation of the next generation mobile phone chips.
The Analog & RF IC Layout Engineer will be part of an experienced layout team. In close cooperation with his/her colleagues he/she will be in charge of the layout of high speed analog and RF circuits and he/she will take up a leading role in the floorplanning and optimization of the system on chip.
He/she is an expert user of Cadence and Mentor tool suites on nanometer RF CMOS and/or RF SOI technology.
The successful candidate will work closely with the RF designers. He/she will take into account the constraints from the designer and will go through iterations with the designer to further optimize the layout from a performance and area perspective.
RF circuit layout experience in the sub 10-Ghz range is mandatory.
The layout engineer should have a good understanding of the different circuit topologies and their constraints for the layout. implementation. Good understanding of the layout rules enables to optimize the implementation.
The senior layout engineer is also capable to perform extraction of parasitics and make the interpretation of these results in view of further optimization.
Required Education and Experience:- Industry Degree qualified (BS or MS EE degree)
- Ample experience with the Cadence OA VirtuosoXL
- Experience with RFIC layout (GHz range) in CMOS technology
- Finfet experience is a major plus.
- Skill automation for layout is preferred.
- Good communication skills & team-player.
- Process oriented, ability to structure the RF layout process
- Continuous strive for improvement in circuits and process.
- Detail oriented and determined
- Relocation to Belgium, if applicable, is strongly recommended.