Description
Job Title: VHDL Design Engineer
Client: Consultancy into Defence sector
Location: High Wycombe
Duration: 3 months
Rate: Negotiable to £350 a day
Please note that this is an SC Cleared role.
VHDL Design Engineer:
The project is to develop an interface module with Ethernet one side and a proprietary comms output the other side, with some DDR3 based data manipulation in the middle. There has been good progress made with the project, so there is work to build on and fortunately the architecture is fairly partitionable.
Send me your CV now and I will call to discuss this role and your situation.