Description
Senior FPGA Backend developer/engineer - Telco 5G
IMPORTANT: You are most welcome to apply if you have permit to work within EU and Sweden.
This assignment is high profile and are in the cutting egde of the new 5G technology!
The task is to be responsible for the top level synthesis and timing closure of the design.
Your task is to be able to drive and be self-driven for the work results.
Wanted background:
- MSc Electrical Eng, Computer science or other similar relevant education
- A minimum of 5 years relevant work experience
Wanted FPGA skills/experience:
- Experience in FPGA Synthesis
- Experience in FPGA floor planning (clock buffer placement)
- Experience in Timing closure for high-frequency FGPA designs
- Experience from multi-clock domain FPGA projects
- Experience in FPGA area optimization
- Experience in Timing constraints development
- Experience in STA
- Experience in Xilinx Vivado tool
- Experience in Intel (Altera) Quartus tool
- Experience in using Signaltap and Chipscope debuggers
- Extensive knowledge about VHDL and Verilog source code.
Not all of above skills are needed for you to apply this assignment
The person should be comfortable to work both on individual tasks as well as in a smaller team
Previous experience at Ericsson/Sony Mobile/or others beneficial
Good spoken and written English