Description
Location: Ghent, Belgium.
Contract: initial 6 months (extendable).
Start date: ASAP.
Desired education level: Master.
Expected level of experience: Medium/Senior.
Relevant skills/competencies:
FPGA development, Xilinx/Vivado and Altera/Quartus
VHDL, digital simulation (ModelSim)
Integration of IP (vendor and proprietary)
Timing closure on >300MHz designs
DDR3/DDR4 Memory controllers
Video interfaces (DisplayPort, HDMI, VbyOne, SDI)
12G+ tranceivers (Xilinx and Altera)
High speed board design
Signal Integrity simulation and measurements
Xilinx Zync PS/PL integration and eSW
Python for component tests"
Knowledge of languages:
English, mandatory.
Dutch, advantageous (the team is Dutch speaking)
Team: 7 engineers developing interface boards and Embedded software for medical LCD displays.
Cooperate closely with the R&D team in Italy.
If this sounds good to you, apply to it or get in touch.
Please note that if you have not been contacted within 7 days, you have not been shortlisted.
Thank you.
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