Description
Next Ventures are urgently seeking an IP design verification Engineer to work for a Swedish multinational networking and telecommunications company based in Lund over a 6 month contract.
The job involves IP design verification within our clients digital ASIC & FPGA projects.
The work includes:
- Verification planning
- Verification specification
- Verification environment (creation/adaptation/maintenance).
- Verification documentation
- Test case creation
- Usage of uVCs
- Usage of reference models (if needed)
- Constrained random testing
- Creation of Coverage Matrix
- Design documentation
- Design verification (regression + development verification)
- Miscellaneous tasks in connection to the block design
A successful candidate is an experienced verification engineer with 5 or more years of IP verification experience. Verification shall be done using System Verilog/UVM
Required skills:
- Education level: Master of Science or similar
- Experience in using the System Verilog/UVM tools and methodology.
- Experience of verification methodology in general.
- Excellent programming skills (SV, VHDL).
- Experience of SW design for an Embedded environment.
- Experience in system level verification is a plus.
- Knowledge in Hardware design/systemization.
- Knowledge in HW design methodology.
- Knowledge in WCDMA, GSM and/or LTE systems.
- Knowledge in programming C, C++ and System C.
- Knowledge about Formal verification is a plus.
- Good Scripting skills using eg Python, TCL and/or Perl.
- Knowledge of reference model development.
- Knowledge about Agile ways of working is a plus
If this role sounds of interest to yourself, please forward your updated CV to (see below) for immediate consideration.