Description
ASIC Design Verification Engineer
Hours/Week: 40 hours/week, M-F
Start Date: ASAP
Assignment Length: 6 months
JOB DUTIES:
- Integration and functional verification for a block of complex IP's for a combined CPU/GPU development effort
- Work closely with a team members to understand and verify new design features
- Debug of Verilog RTL and System Verilog & C/C++ testbench at the IP and/or SOC-level
EXPERIENCE AND EDUCATION:
- 10 or more years of proven verification experience on large ASIC development
- Experience with large SoC build, debug, and general DV is required.
- Knowledgeable in C/C++, OO programming, Verilog, System Verilog, and Scripting languages (Perl, etc)
- Familiar with constrained random verification
- Excellent debug skills, ability to analyze and isolate design/testbench issues using various techniques including waveforms and log files.
- Familiar with hardware modeling and/or assertion-based verification methods
- Excellent written and communication skills
- Background in GPU/CPU architecture along with significant memory system and/or SoC architecture experience is important.
It is the policy of GCR to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, protected veteran or disabled status, or genetic information. GCR is an Equal Opportunity/Affirmative Action Employer and embraces diversity in our employee population.