Description
Verification Engineer - System Verilog - UVM
I'm currently looking out for Verification Engineers experienced in UVM and System Verilog.
Ideally the engineer could interview immediately and start the project at the beginning of February, however if you are coming available in the coming weeks they would consider waiting for the right candidate.
Location: Cambridge
Rate: £53 Contract
Length: 6 months with likelihood of extension.
Key Skills:
Essential - System Verilog, UVM.
Preferable - Experience with CPU systems, Interconnectors and Memory Controllers.
This role is likely to have remote working after a initial period on site.
The engineer must be eligible to work in the UK.
Verification Engineer - System Verilog - UVM
Real Staffing, a trading division of SThree Partnership LLP is acting as an Employment Business in relation to this vacancy