Description
An important organisation within the wireless telecomms industry is looking for a candidate for a FPGA Design Engineer (Senior) role to be a part of a multi-disciplinary team at its facility in Luxembourg to participate in the development activities of the payload for its satellite mission. Please take a look at the information below and let me know what you think.
Location: Luxembourg
Rate: Negotiable (60€-80€ per hour, depending on experience)
Duration: initial 12 months contract (possibilty of extension)
Hours per week: 40 hours
Main requirements:
- M.Sc. in Electronics/Electrical/Telecommunications Engineering or an equivalent qualification.
- Experienced with IPCore design and development for Telecommunication applications in a relevant environment.
- Proven knowledge in wireless VHDL/Verilog for FPGA development
- Experienced with FPGA synthesis tools (ie Xilinx Vivado or Altera Quartus) to work on the RTL code written in VHDL or Verilog.
- Experience with industry standard HDL simulators and functional verification tools.
- In-depth knowledge about processor interfaces, high-speed interfaces, high-speed memory subsystems
- Multi-clock domain design.
- Debugging experience.
- Exposure to current telecommunication standards.
if this sounds appealing, please email me a copy of your CV and I will give you a call to discuss in more detail.
Many thanks,
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