Description
Our Cork based client is urgently searching for 2 RTL Design Engineers to come on board for a 9 month project starting ASAP. This project will see you on the cutting edge of 5G development and would be best suited towards engineers with experience in the design of ASICs and SoCs in advanced digital CMOS processes.We are looking to fill these roles ASAP with interview slots being scheduled for the end of this week.
Requirements:
An in depth knowledge of:
- ASIC design;
- Architecture, RTL design with Verilog/VHDL, low power design techniques, UPF.
- Experience with synthesis, and timing closure.
- Experience with DC, LINT, PTSI, and CDC.
- Knowledge of cryptographic algorithms (SHA, AES, DES).