Description
UVM Verification Engineer - ASAP Start - Cork - up to €60 p/h - 9 monthsOur Cork based client is urgently searching for freelance UVM Verification Engineers to come on board for a 9 month project starting ASAP. This role would be best suited to Verification Engineers with a history of building UVM test benches from scratch.
Requirements:
- Experience in designing and implementing verification environments for complex RTL designs.
- Familiar in the use of class-based hardware verification languages e.g. SystemVerilog or Specman 'e.'
- Building and Supporting a UVM Testbench
- Detailed understanding of Verification methodologies - UVM.
- Knowledge of end-to-end verification processes, from test plan creation through to verification closure.