Description
Our client based in Leuven are seeking a Digital Verification engineer for a long term project working on the design/validation of chips. initially you will be on-boarded fully remote but will be expected be mainly based on site.
Skills/Experience -
You must have experience with designing ASIC
Subsystem and top level verification
Writing Verilog and SystemVerilog RTL
Experience running a simulator ie Cadence, mentor
SystemC/C++/Embedded micro controllers coding and debugging
Revision control systems - SVN/GIT
Many thanks
Michael