Description
Senior ASIC Verification Engineer - System Verilog - Contract - Cambridge
A senior ASIC verification engineer with excellent knowledge of System Verilog is currently required for a contract opportunity in Cambridge.
Successful engineers will be responsible for the verification of high speed ASICs and will have significant experience with ASIC verification methodology and some experience with emulation platforms.
Responsibilities
- Defining and building a modern chip level test bench based on OVM
- Develop test cases and coverage analysis using modern coverage analysis tools
Essential Skills
- Commercial project experience working with OVM methodologies
- Experience with design using System Verilog
- Knowledge of C/C++ and Perl programming would be beneficial
This contract will last an initial 6 months and multiple extensions are likely so apply today with an updated CV to be considered