FPGA/ASIC Design and verification

Stockholm  ‐ Onsite
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Keywords

Description

Our Telecom-client is looking for Digital ASIC/FPGA designers/verifiers for Radio Base Station Units.

Competence:

Master of Science Electrical Engineering, Computer Engineering or equivalent academic qualification.

SystemVerilog

Cadence E -programming

C -programming

VHDL

Specman

Preferred experience

Formal verification/equivalence check

Note

The client is not looking for specific FPGA/ASIC Back End or synthesis experience

Start date
End summer 2012
Duration
Long term assignment
From
Miracle Partners
Published at
17.05.2012
Project ID:
364439
Contract type
Freelance
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