Verification Engineer - System Verilog - Thames Valley

Buckinghamshire  ‐ Onsite
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Keywords

Description

A key client based in Thames Valley is looking for an Verification Engineer with design simulation, prototyping and formal verification methodologies experience. This will be an initial 6-month contract.

The role:
Working in development teams on individual projects, which are creating configurable, re-usable Specman and System Verilog verification environments; implementing the verification methodology of a project; communicating verification strategies and techniques across other projects within the company.

Required Experience:
System Verilog - Verification
Verification experience
Production and review of test specifications
Validation experience including: random, directed random and formal validation (model checking) Verilog or Specman E
Experience of test bench design, ideally using System Verilog or Specman 'e' language

Benefit:
System C
System Verilog - Development
Specman (environment development skills)

If you are interested please send your CV.

Start date
ASAP
Duration
6 months
From
GCS
Published at
07.06.2012
Project ID:
374172
Contract type
Freelance
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