Description
Our client is a hugely popular computer components brand seeking a candidate to provide 1st level support for CAD tools and scripts. S/He will work with Design and Validation Engineers to provide support in the areas of Model Building, RTL Simulation and Validation, Assertion Validation, Code Coverage, Functional Coverage and other Front End related areas. Support includes: RTL design and debugging, RTL and Gate Level Validation, and resolving user errors. There will also be development opportunities to resolve current tool limitations and provide continuous tool improvements. In addition this team is rolling out new capabilities which will require first level support.
OVERVIEW:
- 75 - 80% will be first level support
- 20 - 25% will be tool/script development
REQUIREMENTS:
- Verilog/SystemVerilog
- Design experience (Work or Academic)
- Validation experience (Work or Academic)
- Simulation and Validation tools such as Synopsys VCS or Mentor Graphic's Modelsim or Questa
- Software Programming knowledge
Additional Skills (Nice to Have):
- Perl
- Python
- C/C++
- Verilog VPI/DPI
- BS or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science
- Verdi/Debussy
- SystemC
Estimated length of sssignment: 6months +
Number of positions available: 2
Estimated hours per week: 40 hourrs (standard hours: 8:00AM - 5:00PM)
Occasional overtime needed (with approval)
% of travel required: none
Please include a daytime phone number where you can best be reached with your Resume. Please also include a brief cover letter outlining your experience as related to this job requirement. CompuCom is an Equal Opportunity Employer. No 3rd party/recruiters please.