Contract FPGA Design Engineer - Verilog - Virtex

Description

40-45 p/h
FPGA design, FPGA, Cambridge, ASIC, Xilinx, Virtex, VHDL, Digital, Verilog

Based in Cambridge, we have a requirement for an FPGA Design Contract Engineer for a period of 5 months initially. The successful contractor will have a proven background in FPGA design with the ability to build and support the implementation of ASIC prototypes on HAPs emulators. Please respond now if you are currently or soon to be available for contract work.

Key requirements include:
Experience of Verilog and System Verilog(desirable)
Synplify Premier/Pro and Xilinx design flow.
Experience of entire FPGA design flow including constraints and debugging.
Proven ability to map complex designs to Virtex-5, Virtex-6, Virtex-7 desirable.
Hardware board design knowledge and ASIC experience would be an advantage.

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