Description
Our leading international Semiconductor partner is looking for V&V Lead Engineer.Verification/Validation Lead Engineer is responsible for performing the Analog/Mixed Signal (AMS) V&V simulations and measurements of Digital and AMS product designs, sub-systems, purchased and newly developed IP for the Automotive Market, specifically In-Vehicle Networking products.
MAIN RESPONSIBILITIES:
Specify, plan, execute and report the overall V&V strategy of products and IP, to proof the functional, structural and parametrical correctness before IC Mask Ordering and before product release.
Check gaps/overlap of test specifications for the different test levels
Work closely together with Architects (System, IC, SW) to understand the overall product concept and to discuss the V&V approach and results.
Support the V&V Engineers in setting up their detailed test specifications and plan, analysing defect causes and defect prevention measures.
Participate in Change Control Board, simulations, reviews, inspections, walk-throughs from the V&V perspective
Analysing defect causes and suggesting defect prevention measures
Definition of the V&V simulation infrastructure, including, test benches, Verification IP, lab test infrastructure (both HW and SW), prototyping (FPGA and/or virtual prototyping).
Lead Competence development of V&V simulations and V&V measurements
Coaching/training Verification and Validation engineers
Targeting re-use of V&V components, Infrastructure, tooling and SW.
REQUIRED SKILLS:
Excellent communicator, team player, analytical skills and helicopter view.
At least 10 years of working experience in AMS IC Design and/or Verification/Validation and a master degree (or similar level acquired by experience) in electronics or information engineering.
To ease the discussion with the architects and developers, knowledge of AMS IC development process, flows and IC application is a must.
Extensive knowledge of and hands-on experience with V&V simulation and measurements methods, different V&V strategies, levels and tools.
Hands-on experience with Virtual and/or FPGA prototyping and digital verification methodologies;
Experience with Analog Mixed signal design and or verification is a big plus. Must have at least some fundamental knowledge of analog design principles and tooling.
Knowledge of CMMi/TMMi, V-diagram, tools for requirements management
Good skills in Verilog (AMS) and/or VHDL, Tcl and/or Perl, Linux/Unix Scripting, Pyton and/or C.
Experience with SystemC, System Verilog, XML, Ocean, Cadence EDA tooling is a plus.