Description
We are looking for a
Verification Engineer (m/f)
Reference: -en
Start: asap
Duration: 6 MM++
Place: in Styria (Austria)
Branch: Herstellung von sonstigen elektronischen Bauelementen
Your tasks:
- IC develpment, presilicon verification on block and top Level employing UVM methodology
- Plan verification workpackages
- Define and implement verification environment
- Develop block and system-level test cases
- Execute verification and analyse verification results, propose design changes, regression test analysis including time constraint solving
- Prepare test patterns and post silicon validation Support quality and yield engineering activities with pre silicon verification methods
Your qualifications
- Good understanding of embedded processor based SoC architecture
- Strong competence in assertion based, coverage driven and formal verification, System Verilog, UVM / OVM
- Experience in C#, Make and proficient in scripting using perl, Tcl
- Experience in definition of verification environments and flows
- English
Skills:
- Hardware developer