Description
Prefer Master's degree in Electrical Engineering or related fieldsExperience:
. Verilog coding.
. Simulation test bench development/verification
. Logic synthesis and static timing analysis
. Knowing Timing model generation.
. IP integration and SOC Design flow
. Familiar backend tool is a plus.
Design and verify integrated storage SOCs for storage systems.
. Understand customer requirements, technical standard such as DDR, PCIE, Serial ATA, Serial Attached SCSI.
. Develop timing constraints.
. Realize the design in FPGA platform and verify the design in a real system.
. Work on logic synthesis and static timing analysis.
. Work with back-end and layout engineers on chip-level floor-planning, power planning, macro and standard cell placement, clock tree synthesis, design rule checks and post-layout timing analysis.
. Create SCAN and Functional test patterns for production test.
. Create Boundary SCAN test patterns for production test.
. Generate timing model.
. Conduct test plans to identify functional problems and performance issues with the silicon during the chip evaluation process.