Sr. ASIC Design Verification Engineer

Description

Job description

Responsibilities:

Responsible to define and implement verification architectures for mixed signal data communications semiconductors

Desired Skills and Experience

Requirements:

Full understanding of digital design verification methodologies and tools including:

• Expertise in creating verification infrastructure using higher level language like system verilog/specman-e etc.
• Must be able to create testplans describing coverage points.
• Expertise in creating random and directed tests to achieve coverage goals.
• Experience in gate level simulation with SDF
• Experience in diagnosing silicon issue in the lab.
• Desirable to have used high level verification languages like UVM, OVM
• Desirable to have experience with Ethernet, 10GBase-T, PHYS, Switches, and MACs

Education & Experience:

• BS or MS (preferred) in Electrical Engineering, Computer Science, or related
• Minimum of 6-10 years of hands-on experience