Description
Verification Engineer - (UVM, VHDL,C)An exciting opportunity for an experienced Verification Engineer to work a 6 month contract in The Netherlands for a World Leading Semiconductor Company.
As a Verification Engineer you'll be part of an Automotive team working on the next generation of in-vehicle networking products.
Responsibilities shall include:
*Implementing IP level UVM tests
*Debugging and provide root cause analysis for any defects.
*Conducting verification and validation simulations including test benches.
Essential Skills:
*5 years' minimum experience of IP level verification using UVM or Specman.
*Coding experience with either System Verilog, VHDL or similar.
*Ethernet domain experience.
*C, Tcl, Perl Programming experience.
*AMS verification experience (desirable)
*PSL formal verification experience (desirable)
Start Date: ASAP
Salary: Negotiable based on experience
If this is of interest to you then please get in touch with an up to date CV and I would be happy to arrange telephone interview
Key Words: Verification/Hardware/Software/Validation/Automotive/Tcl/Perl/UVM/Specman/IP/Cadence/Design/C/VHDL/System/Verilog/Engineer