Description
Our leading international Semiconductor partner is looking for a Digital Verification Engineer. As a Verification Engineer you will be part of a team, which is responsible for performing the Digital V&V simulations of next generation Automotive Ethernet Switch products for Automotive In-Vehicle Networking products.MAIN RESPONSIBILITIES :
• The Digital Verification Engineer is responsible for the setup and execution of IP level UVM tests on moderate to high complexity IP’s and or top level IC’s
• Work closely with Architects (System, IC, SW) to understand the overall product concept and to discuss the Verification approach and results.
• Analysing defect causes, debugging, rootcause analysis of unexpected simulation results
• Definition of the V&V simulation infrastructure, including, test benches, Verification IP
• Coaching/training other Verification engineers
• Targeting re-use of V&V components, Infrastructure, tooling and SW.
REQUIRED SKILLS:
• Experience in IP level functional verification using UVM methodology/ Specman
• Experience in coding with System Verilog, Verilog and VHDL
• Experience in programming C, tcl and perl
• Experience with Cadence design environment
• Experience with Ethernet domain specific IP’s is big plus
• Basic knowledge of digital systems
• Able to make a clear documentation of designs
• Clear and concise communication
• Excellent problem solving skills
• Team player, self starter
• Languages: English, both verbal and in writing.
NICE TO HAVE SKILLS
• Experience with domain specific IP’s (e.g. Ethernet, MII, RMII, GMII, UART, SPI, AHB, APB, I2C)
• Experience in writing verification software for hardware verification
• Experience with back-annotated verification
• Experience with PSL for formal verification
• Experience with AMS verification
• Experience with linting (e.g. Spyglass)